Universitat Autònoma de Barcelona
Digital Systems: From Logic Gates to Processors
Universitat Autònoma de Barcelona

Digital Systems: From Logic Gates to Processors

Elena Valderrama
Jean-Pierre Deschamps
Lluis Terés

位教师:Elena Valderrama

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深入了解一个主题并学习基础知识。
4.3

(847 条评论)

中级 等级
需要一些相关经验
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3 周 在 10 小时 一周
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91%
大多数学生喜欢此课程

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作业

17 项作业

授课语言:英语(English)

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该课程共有12个模块

This module is includes a number of general explanations about how the course will run and about the virtual machine you should install on your computer to answer the different quizzes.

涵盖的内容

1个视频11篇阅读材料

This module presents a series of tests you can use to check your level of knowledge about numbering systems and the use of pseudocode to describe algorithms.

涵盖的内容

2个视频2篇阅读材料2个作业

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b> <br/><br/>This module is an introduction to Digital Systems. Here you will find:<ol><li>A set of videos_L covering issue 1 and the corresponding exercises, </li><li>Two videos_P introducing the processor that we will design along the course, and</li><li>Some video-based explanations; a wiki and some FAQs about how VerilUOC_Desktop tool functions.<br/> You will have to use VerilUOC_Desktop in the next module</li></ol> Read the "Lesson Index" in the "Index and PDF files" section and the "README" in the VerilUOC_Desktop section for more information.

涵盖的内容

5个视频3篇阅读材料2个作业

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b> <br/><br/>This module introduces combinational circuits, logic gates and boolean algebra, all of them items necessary to design simple combinational circuits.<br/> Read the "Index of lessons" for more information. <br/><br/><b>To solve the exercises in this module you will need to use VerilUOC_Desktop. Look at the module "VerilUOC_Desktop tools" to learn how to use it.</b>

涵盖的内容

5个视频3篇阅读材料2个作业

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>From this module you will need to use VerilUOC_Desktop to do some of the exercises in the quizzes. VerilUOC_Desktop is a software package based on Logisim, enhanced with a number of modules to enable:<ul><li>Enter Boolean equations (BoolMin),</li><li>Enter digital circuits and check them according the problem statement (VerilCirc), and</li><li>Enter chronograms (time-charts) and check that they are correct (VerilChart).</li></ul>This section contains two videos explaining how these three tools work. By now you only need to use VerilCirc and BoolMin, so if you are pushed for time, you might postpone VerilChart for later. Obviously, it is impossible to cover in these two videos all eventualities you can find while working with VerilUOC_Desktop tools. In case of doubt, look at the VerilUOC_Desktop wiki, look at the FAQs or post your problems in the forums. There are specific forums for VerilCirc, BoolMin and VerilChart.

涵盖的内容

2个视频3篇阅读材料

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>We continue the study of combinational circuits. While in the previous module we were working on the classical design techniques of combinational circuits, this one is focused on other issues such as a brief introduction to computer aided design tools (CAD tools), or the direct synthesis of combinational circuits from its algorithmic description.<br/> Read the "Lesson index" for more information. <br><br/><b>To solve the exercises in this module VerilUOC_Desktop is needed. </b>Remember that the module "VerilUOC_Desktop tols" contains all the information you need about this tool.

涵盖的内容

5个视频3篇阅读材料2个作业

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>Arithmetic circuits are an essential part of many digital circuits and thus deserve a particular treatment. <ul><li> The first part of this module presents some implementations of the basic arithmetic operations. Only operations with naturals (non-negative integers) are considered. </li><li>The second part of this module introduces the basics of VHDL with the goal of providing enough knowledge to understand its usage throughout this course and start developing basic hardware models.</li></ul>

涵盖的内容

10个视频9篇阅读材料1个作业

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>This is the first module dedicated to Sequential Circuits (Digital Systems with Memory).<br/><b>To solve the quizzes you will need VerilUOC_Desktop</b>.

涵盖的内容

7个视频3篇阅读材料2个作业

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>This second module dedicated to Sequential Circuits deals with particular sequential circuits that are building blocks of larger circuits, namely registers, counters and memory blocks.

涵盖的内容

4个视频3篇阅读材料2个作业

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>This module deals with two topics: <ol><li>In previous lessons, the relation between algorithms (programming language structures) and combinational circuits has been commented. This relation also exists between algorithms and sequential circuits. We will explore this relation in the current module.</li><li>The second topic we will see is the definition and VHDL modelling of Finite State Machines.</li></ol>

涵盖的内容

5个视频4篇阅读材料2个作业

<b><font size=4 color=#B22222><b>Click on "v More" to read the purpose of this module</b></font> </b><br/><br/>This last module presents some basic information about manufacturing technologies, as well as about implementation strategies, and synthesis and implementation tools.

涵盖的内容

4个视频2篇阅读材料2个作业

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涵盖的内容

3篇阅读材料

位教师

授课教师评分
4.4 (137个评价)
Elena Valderrama
Universitat Autònoma de Barcelona
2 门课程145,691 名学生
Jean-Pierre Deschamps
Universitat Autònoma de Barcelona
2 门课程145,691 名学生
Lluis Terés
Universitat Autònoma de Barcelona
2 门课程145,691 名学生

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