Design of Digital Circuits with VHDL Programming

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Design of Digital Circuits with VHDL Programming

Ce cours fait partie de Spécialisation "Chip based VLSI design for Industrial Applications"

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à 10 heures par semaine

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Catégorie : Simulation and Simulation Software
Catégorie : Dataflow
Catégorie : Verification And Validation
Catégorie : Simulations
Catégorie : Test Script Development
Catégorie : Computational Logic
Catégorie : Schematic Diagrams
Catégorie : Hardware Design

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Il y a 4 modules dans ce cours

This course is designed to provide a comprehensive understanding of digital circuit design using VHDL programming with Xilinx ISE. Participants will learn the fundamentals of VHDL, simulation modeling, and design methodologies for digital circuits, including combinational and sequential circuits. Practical exercises using Xilinx ISE will enhance hands-on skills in circuit implementation, simulation, and analysis.

This module provides a comprehensive introduction to VHDL (VHSIC Hardware Description Language) programming, focusing on digital circuit design and simulation. Participants will learn about VHDL design elements, data objects, modeling styles, delay type modeling, operators, concurrent statements, process statements, subprograms, data flow description, behavioral description, attributes, and logic operations. The module aims to simplify VHDL programming concepts and techniques, making it accessible for beginners and providing a strong foundation for digital circuit design using VHDL.

Inclus

16 vidéos5 lectures1 devoir

16 vidéosTotal 120 minutes

About the Specialization3 minutes
About the Course5 minutes
Importance of VHDL Programming Language in Digital Design10 minutes
VHDL Design and Modelling Styles - Part 14 minutes
VHDL Design and Modelling Styles - Part 210 minutes
Basic Design Elements of VHDL8 minutes
VHDL - Object9 minutes
Structural Description Using VHDL10 minutes
VHDL - Configuration10 minutes
VHDL - Operators and Process Statements7 minutes
VHDL - Conditional Statements and Loops10 minutes
Dataflow Description Using VHDL6 minutes
Behavioral Description Using VHDL8 minutes
Attributes in VHDL8 minutes
VHDL Programming for Logic Operations - Part 15 minutes
VHDL Programming for Logic Operations - Part 26 minutes

5 lecturesTotal 50 minutes

Specialization Reading10 minutes
Course Reading10 minutes
Course Glossary10 minutes
VHDL - Data Types10 minutes
VHDL - User Defined Data Types10 minutes

1 devoirTotal 30 minutes

Assessment on VHDL Programming Made Easy 30 minutes

This module provides a comprehensive exploration of digital combinational circuits design using VHDL programming within the Xilinx ISE Design Suite environment. Participants will delve into fundamental concepts such as AND gates, half adders, full adders, multiplexers, demultiplexers, encoders, decoders, comparators, barrel shifters, and binary-to-BCD and binary-to-Gray code converters. The module covers various VHDL modeling styles including structural, dataflow, and behavioral modeling, enabling a deep understanding of circuit design and simulation.

Inclus

51 vidéos1 devoir

51 vidéosTotal 455 minutes

Xilinx ISE Installation and its Design Flow - Part 18 minutes
Xilinx ISE Installation and its Design Flow - Part 27 minutes
Xilinx ISE Installation and its Design Flow - Part 311 minutes
Structural Modelling Style in VHDL with Half Adder - Part 19 minutes
Structural Modelling Style in VHDL with Half Adder - Part 28 minutes
Structural Modelling Style in VHDL with Half Adder - Part 38 minutes
Structural Modelling Style in VHDL with Half Adder - Part 48 minutes
Dataflow Modelling Style in VHDL with Half Adder - Part 19 minutes
Dataflow Modelling Style in VHDL with Half Adder - Part 28 minutes
Behavioral Modelling Style in VHDL with Half Adder - Part 110 minutes
Behavioral Modelling Style in VHDL with Half Adder - Part 28 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 114 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 210 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 37 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 48 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 58 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 67 minutes
Design of Full Adder Using Various Modelling Styles in VHDL - Part 711 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 113 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 29 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 39 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 46 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 58 minutes
Design of 4-bit Ripple Carry Adder (RCA) Using Various Modelling Styles in VHDL - Part 67 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 110 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 210 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 312 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 48 minutes
Design of Multiplexer Using Various Modelling Styles in VHDL - Part 58 minutes
Design of Demultiplexer Using Various Modelling Styles in VHDL - Part 112 minutes
Design of Demultiplexer Using Various Modelling Styles in VHDL - Part 26 minutes
Design of Demultiplexer Using Various Modelling Styles in VHDL - Part 311 minutes
Design of Demultiplexer Using Various Modelling Styles in VHDL - Part 412 minutes
Design of Encoder Using Various Modelling Styles in VHDL - Part 19 minutes
Design of Encoder Using Various Modelling Styles in VHDL - Part 25 minutes
Design of Encoder Using Various Modelling Styles in VHDL - Part 39 minutes
Design of Encoder Using Various Modelling Styles in VHDL - Part 412 minutes
Design of Decoder Using Various Modelling Styles in VHDL - Part 112 minutes
Design of Decoder Using Various Modelling Styles in VHDL - Part 25 minutes
Design of Decoder Using Various Modelling Styles in VHDL - Part 310 minutes
Design of Decoder Using Various Modelling Styles in VHDL - Part 411 minutes
Design of 4-bit Comparator Using Various Modelling Styles in VHDL - Part 110 minutes
Design of 4-bit Comparator Using Various Modelling Styles in VHDL - Part 210 minutes
Design of 4-bit Comparator Using Various Modelling Styles in VHDL - Part 38 minutes
Design of 4-bit Comparator Using Various Modelling Styles in VHDL - Part 49 minutes
Design of 8-bit Barrel Shifter Using VHDL - Part 112 minutes
Design of 8-bit Barrel Shifter Using VHDL - Part 27 minutes
Design of 4-bit Binary to BCD Converter in VHDL - Part 18 minutes
Design of 4-bit Binary to BCD Converter in VHDL - Part 25 minutes
Design of 4-bit Binary to Grey Code Converter in VHDL - Part 17 minutes
Design of 4-bit Binary to Grey Code Converter in VHDL - Part 26 minutes

1 devoirTotal 30 minutes

Assessment on Design of Digital Combinational Circuits with VHDL Programming Using Xilinx ISE30 minutes

This module focuses on the design and implementation of digital sequential circuits using VHDL programming within the Xilinx ISE-I environment. Participants will delve into fundamental sequential circuit components such as D latch, D flip-flop, SR flip-flop, JK flip-flop, T flip-flop, shift registers, counters, and FIFO memories. Various VHDL modeling styles including structural, dataflow, and behavioral modeling will be utilized to develop and analyze the functionality of these sequential circuits.

Inclus

20 vidéos1 devoir

20 vidéosTotal 173 minutes

Design of D Latch Using Various Modelling Styles in VHDL - Part 110 minutes
Design of D Latch Using Various Modelling Styles in VHDL - Part 26 minutes
Design of D Latch Using Various Modelling Styles in VHDL - Part 310 minutes
Design of D Latch Using Various Modelling Styles in VHDL - Part 411 minutes
Design of D Flip Flop using VHDL13 minutes
Design of SR Flip Flop using VHDL - Part 18 minutes
Design of SR Flip Flop using VHDL - Part 27 minutes
Design of JK Flip Flop using VHDL - Part 17 minutes
Design of JK Flip Flop using VHDL - Part 29 minutes
Design of T Flip Flop using VHDL11 minutes
Design of 5-bit Shift Register Using VHDL Part 112 minutes
Design of 5-bit Shift Register Using VHDL Part 26 minutes
Design of Universal Shift Register using VHDL - Part 110 minutes
Design of Universal Shift Register Using VHDL - Part 29 minutes
Design of 4-bit Counter Using VHDL - Part 17 minutes
Design of 4-bit Counter Using VHDL - Part 26 minutes
Design of First in First Out (FIFO) Memory Using VHDL Part 17 minutes
Design of First in First Out (FIFO) Memory Using VHDL Part 26 minutes
Design of Asynchronous First in First Out (FIFO) Memory Using VHDL Part 111 minutes
Design of Asynchronous First in First Out (FIFO) Memory Using VHDL Part 26 minutes

1 devoirTotal 30 minutes

Assessment on Design of Digital Sequential Circuits with VHDL Programming Using Xilinx ISE-I30 minutes

This module delves into the design and implementation of digital sequential circuits using VHDL programming techniques within the Xilinx ISE-II environment. Participants will explore various sequential circuit components such as Single Port RAM, Dual Port RAM, sequence detectors (including Mealy and Moore machines), and a digital model of a vending machine. The module emphasizes hands-on learning, combining theoretical concepts with practical design and simulation exercises to develop a comprehensive understanding of digital sequential circuit design methodologies.

Inclus

23 vidéos1 devoir

23 vidéosTotal 182 minutes

Design of Single Port RAM using VHDL - Part 17 minutes
Design of Single Port RAM using VHDL - Part 28 minutes
Design of Dual Port RAM using VHDL - Part 17 minutes
Design of Dual Port RAM using VHDL - Part 29 minutes
Design of Mealy Non-overlapping 3-bit Sequence Detector using VHDL - Part 17 minutes
Design of Mealy Non-overlapping 3-bit Sequence Detector using VHDL - Part 27 minutes
Design of Mealy Non-overlapping 3-bit Sequence Detector using VHDL - Part 36 minutes
Design of Mealy Non-overlapping 5-bit Sequence Detector using VHDL - Part 111 minutes
Design of Mealy Non-overlapping 5-bit Sequence Detector using VHDL - Part 26 minutes
Design of Mealy Overlapping 3-bit Sequence Detector using VHDL - Part 19 minutes
Design of Mealy Overlapping 3-bit Sequence Detector using VHDL - Part 27 minutes
Design of Mealy Overlapping 5-bit Sequence Detector Using VHDL Part 110 minutes
Design of Mealy Overlapping 5-bit Sequence Detector Using VHDL Part 27 minutes
Design of Moore Non-overlapping 3-bit Sequence Detector Using VHDL Part 112 minutes
Design of Moore Non-overlapping 3-bit Sequence Detector Using VHDL Part 26 minutes
Design of Moore Non-overlapping 5-bit Sequence Detector using VHDL - Part 110 minutes
Design of Moore Non-overlapping 5-bit Sequence Detector using VHDL - Part 26 minutes
Design of Moore Overlapping 3-bit Sequence Detector Using VHDL Part 110 minutes
Design of Moore Overlapping 3-bit Sequence Detector Using VHDL Part 26 minutes
Design of Moore Overlapping 5-bit Sequence Detector using VHDL - Part 1 9 minutes
Design of Moore Overlapping 5-bit Sequence Detector using VHDL - Part 26 minutes
Design of Vending Machine Using VHDL Part 18 minutes
Design of Vending Machine Using VHDL Part 210 minutes

1 devoirTotal 30 minutes

Assessment on Design of Digital Sequential Circuits with VHDL Programming Using Xilinx ISE-II30 minutes

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